1. Field of the Invention
The present invention relates to semiconductor techniques, and more specifically, to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
With the development of integrated circuit technology, the dimension of a semiconductor device has become increasingly smaller. In order to control short-channel effect, a smaller device dimension requires further improving gate capacitance. Generally, gate capacitance is improved by decreasing the thickness of a gate dielectric layer (usually, silicon oxide (SiO2)) that is between a gate and a substrate. However, this may increase gate leakage current and decrease the device reliability. Moreover, with the shrinkage of critical dimension, it is difficult to further reduce the thickness of the gate dielectric layer.
Thus, in the present very large scale integrated circuit (VLSI) process, the high dielectric constant (high-K) metal gate (HK-MG) scheme has gradually become a mainstream technology. In the HK-MG scheme, a material of high dielectric constant, which has a higher dielectric constant and a better field effect characteristic than silicon oxide, is used as the material of the gate dielectric layer instead of silicon oxide. In order to be compatible with the high-K material, a metal gate is usually employed to replace a traditional polysilicon gate.
Currently, an Al gate is mostly used as the metal gate in the HK-MG scheme. During the manufacturing process of a semiconductor device, for electrical connection of the gate, generally, a dielectric layer is firstly deposited on the gate and then etched to form a contact hole connected to the gate. Thus, the contact hole etching needs to be performed until reaching the surface of the Al gate. However, the inventor has found that the surface of aluminium is easy to be oxidized during the process of depositing a dielectric layer on the gate, which results in the formation of an aluminium oxide (Al2O3) film on the surface of aluminium. This aluminium oxide film interrupts the contact hole etching such that the etching stops on the aluminium oxide film and cannot reach aluminium in the gate, thereby failing to form an effective electrical connection for the Al gate.
FIGS. 1A-1C are diagrams illustrating the above process for forming a gate contact hole according to the conventional HK-MG technique.
Firstly, as shown in FIG. 1A, a substrate 102 with a first dielectric layer 110 and a gate 104 is provided, wherein the gate 104 is embedded in the first dielectric layer 110. The substrate 102 can be silicon or any other suitable material. The first dielectric layer 110 on the substrate 102 can be formed from any suitable material, such as silicon oxide. Optionally, a stop layer (not shown) formed from a material such as silicon nitride can be formed between the substrate 102 and the first dielectric layer 110, which can help control the etching of contact holes for the source and the drain. A gate dielectric layer 106 of high-k can be formed between the gate 104 and the substrate 102, which can be formed from any suitable high-k material such as hafnium oxide or zirconium oxide. An isolating layer (not shown) formed from a material such as titanium or titanium nitride can be optionally formed between the gate 104 and the gate dielectric layer 106. Side wall spacers 108 are usually provided on both sides of the gate 104. Optionally, the gate 104 and an upper surface of the first dielectric layer 110 can be flush with each other by way of processes like chemical mechanical polishing (CMP). The gate 104 can be formed from any suitable metal and/or a combination of metals, and the upper portion of the gate 104 is aluminium in this example. In order to obtain the structure shown in FIG. 1A, either the gate-first scheme or the gate-last scheme can be employed. Since these two schemes are known by one of ordinary skill in the relevant art, the details thereof will be omitted for the sake of not obscuring the major ideas of the present invention.
In the conventional process, after obtaining the structure shown in FIG. 1A, a second dielectric layer 120 is deposited thereon, as shown in FIG. 1B. Then, the second dielectric layer 120 is etched to form a gate contact hole 130, as shown in FIG. 1C. However, during the process of depositing the second dielectric layer 120, or if the structure shown in FIG. 1A is exposed to air for a long time, the metal (Al in this example) of the upper surface of the gate 104 is prone to be oxidized, thereby forming an oxidation film (aluminium oxide film in this example) 122 on the upper surface of the gate. Usually, the contact hole etching process mainly for removing the material of the second dielectric layer cannot remove this oxidation film 122. Therefore, during the process of the contact hole etching in FIG. 1C, the etching stops at this oxidation film 122 and cannot continue, and consequently the contact hole fails to reach the aluminium in the gate. Moreover, since the conductivity of aluminium oxide is very poor, the gate cannot be effectively electrically connected to the contact that is filled in the contact hole and thus suffers the “open” issue. This issue is not limited to Al gate. Actually, the same issue will occur so long as the metal of the surface of the gate metal is easy to be oxidized.
Therefore, it is necessary to propose a new technology to address the above issue.